package miggy.cpu.instructions.bitshift;

import miggy.cpu.*;
import miggy.api.cpu.*;
import miggy.cpu.operands.OperandFactory;
import miggy.SystemModel;

/*
//  Miggy - Java Amiga MachineCore
//  Copyright (c) 2008, Tony Headford
//  All rights reserved.
//
//  Redistribution and use in source and binary forms, with or without modification, are permitted provided that the
//  following conditions are met:
//
//    o  Redistributions of source code must retain the above copyright notice, this list of conditions and the
//       following disclaimer.
//    o  Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the
//       following disclaimer in the documentation and/or other materials provided with the distribution.
//    o  Neither the name of the Miggy Project nor the names of its contributors may be used to endorse or promote
//       products derived from this software without specific prior written permission.
//
//  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
//  INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
//  DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
//  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
//  SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
//  WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
//  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
// $Revision: 21 $
*/
public class LSL_mem implements Instruction
{
	public final void register(InstructionSet set)
	{
		int base = 0xe3c0;
		for(int mode = 2; mode < 8; mode++)
		{
			for(int reg = 0; reg < 8; reg++)
			{
				if(mode == 7 && reg > 1)
					break;

				set.add(base + (mode << 3) + reg, this);
			}
		}
	}

	public int execute(int opcode)
	{
		//todo: fix - this is ASL_mem
		Size size = Size.Word;
		Operand dst = OperandFactory.fetchOperand((opcode & 0x0038) >> 3, (opcode & 0x007), false, size);

		int dstval = dst.get(size);

		if((dstval & 0x8000) != 0)
		{
			//carry set
			SystemModel.CPU.setFlag(CpuFlag.C);
			SystemModel.CPU.setFlag(CpuFlag.X);

			if((dstval & 0x4000) != 0)
				SystemModel.CPU.setFlag(CpuFlag.V);
			else
				SystemModel.CPU.clrFlag(CpuFlag.V);
		}
		else if((dstval & 0x4000) != 0)
		{
			SystemModel.CPU.setFlag(CpuFlag.V);
			SystemModel.CPU.setFlag(CpuFlag.N);

			SystemModel.CPU.clrFlag(CpuFlag.C);
			SystemModel.CPU.clrFlag(CpuFlag.X);
		}
		else
		{
			SystemModel.CPU.clrFlag(CpuFlag.V);
			SystemModel.CPU.clrFlag(CpuFlag.C);
			SystemModel.CPU.clrFlag(CpuFlag.X);
			SystemModel.CPU.clrFlag(CpuFlag.N);
		}

		dstval <<= 1;
		dstval &= 0xffff;

		if(dstval == 0)
		{
			SystemModel.CPU.setFlag(CpuFlag.Z);
		}
		else
		{
			SystemModel.CPU.clrFlag(CpuFlag.Z);
		}

		dst.put(dstval, size);
		return 8 + dst.timing(size);
	}

	public DecodedInstruction disassemble(int address, int opcode)
	{
		Size size = Size.Word;
		DecodedInstructionImpl di = new DecodedInstructionImpl("lsl", opcode, address, size);
		di.setSrc(OperandFactory.valueOf(address + 2, (opcode & 0x0038) >> 3, (opcode & 0x007), true, size));
		return di;
	}
}
